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64K 32K 16K
FEATURES
X25643/45 X25323/25 X25163/65
DESCRIPTION
8K x 8 Bit 4K x 8 Bit 2K x 8 Bit
Programmable Watchdog Timer & VCC Supervisory Circuit w/Serial E2PROM
* Programmable Watchdog Timer * Low Vcc Detection and Reset Assertion --Reset Signal Valid to Vcc=1V * Save Critical Data With Block LockTM Protection --Block LockTM Protect 0, 1/4, 1/2 or all of Serial E2PROM Memory Array * In Circuit Programmable ROM Mode * Long Battery Life With Low Power Consumption --<50A Max Standby Current, Watchdog On --<1A Max Standby Current, Watchdog Off --<5mA Max Active Current during Write --<400A Max Active Current during Read * 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation * 2MHz Clock Rate * Minimize Programming Time --32 Byte Page Write Mode --Self-Timed Write Cycle --5ms Write Cycle Time (Typical) * SPI Modes (0,0 & 1,1) * Built-in Inadvertent Write Protection --Power-Up/Power-Down Protection Circuitry --Write Enable Latch --Write Protect Pin * High Reliability * Available Packages --14-Lead SOIC (X2564x) --14-Lead TSSOP (X2532x, X2516x) --8-Lead SOIC (X2532x, X2516x) BLOCK DIAGRAM
SI SO SCK CS DATA REGISTER COMMAND DECODE & CONTROL LOGIC RESET CONTROL X - DECODE LOGIC
These devices combine three popular functions, Watchdog Timer, Supply Voltage Supervision, and Serial E2PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET/RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user's system is protected from low voltage conditions by the device's low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET/RESET is asserted until Vcc returns to proper operating levels and stabilizes. The memory portion of the device is a CMOS Serial E2PROM array with Xicor's Block LockTM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.
PAGE DECODE LOGIC 32 SERIAL E2PROM ARRAY 8
RESET/RESET
STATUS REGISTER
VCC
LOW VOLTAGE SENSE
WATCHDOG TIMER
WP
PROGRAMMING, BLOCK LOCK & ICP ROM CONTROL
HIGH VOLTAGE CONTROL
Characteristics subject to change without notice
7036 FRM 01
(c)Xicor, Inc. 1994, 1995, 1996 Patents Pending 7049 -1.0 6/20/97 T0/C0/D0 SH
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PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the device is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low and the nonvolatile bit WPEN is "1", nonvolatile writes to the device's Status Register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes to the Status Register operate normally. If an internal Status Register Write Cycle has already been initiated, WP going low while WPEN is a "1" will have no effect on this write. Subsequent write attempts to the Status Register under these conditions will be disabled. The WP pin function is blocked when the WPEN bit in the Status Register is "0". This allows the user to install the device in a system with WP pin grounded and still be able to program the Status Register. The WP pin functions will be enabled when the WPEN bit is set to a "1". Reset (RESET/RESET) RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. RESET/ RESET will also go active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time-out period. A falling edge of CS will reset the Watchdog Timer.
2
PIN CONFIGURATION
14-LEAD SOIC NC CS CS 0.345" SO WP VSS NC 1 2 3 4 5 6 7 0.244" 8-LEAD SOIC CS SO 0.197" WP VSS 1 8 X25323/25 7 2 X25163/65 3 6 4 0.244" 5 V CC RESET/RESET SCK SI X25643/45 14 13 12 11 10 9 8 NC V CC V CC RESET/RESET SCK SI NC
Not to Scale
14-LEAD TSSOP CS SO NC 0.200" NC NC WP VSS 1 2 14 13 V CC RESET/RESET NC NC NC SCK SI
7036 FRM 02
3 X25323/25 12 4 X25163/65 11 5 6 7 0.177" 10 9 8
PIN NAMES Symbol CS SO SI SCK WP VSS VCC
RESET/RESET
Description Chip Select Input Serial Output Serial Input Serial Clock Input Program Protect Input Ground Supply Voltage Reset Output
7036 FRM T01
X25643/45 X25323/25 X25163/65
PRINCIPLES OF OPERATION The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the bus and asserts RESET/RESET output if there is no bus activity within user programmable time-out period or the supply voltage falls below a preset minimum Vtrip. The device contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows: 7 6 5 4 3
BL1
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress. The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL=1, the latch is set HIGH and when WEL=0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The Block Lock bits, BL0 and BL1, set the level of Block LockTM Protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the E2PROM array. Any portion of the array that is Block Lock Protected can be read but not written. It will remain protected until the BL bits are altered to disable Block Lock Protection of that portion of memory.. Status Register Bits BL1 BL0
0 0 1 1 0 1 0 1
Array Addresses Protected X2564x
None
X2532x
None
X2516x
None
$1800-$1FFF $0C00-$0FFF $0600-$07FF $1000-$1FFF $0800-$0FFF $0400-$07FF $0000-$1FFF $0000-$0FFF $0000-$07FF
7036 FRM T03
2
BL0
1
WEL
0
WIP
7036 FRM T02
WPEN FLB
WD1 WD0
Table 1. Instruction Set Instruction Name
WREN SFLB WRDI/RFLB RSDR WRSR READ WRITE
Instruction Format*
0000 0110 0000 0000 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Operation Set the Write Enable Latch (Enable Write Operations) Set Flag Bit Reset the Write Enable Latch/Reset Flag Bit Read Status Register Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address
7036 FRM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time-out (Typical)
1.4 Seconds 600 Milliseconds 200 Milliseconds Disabled
7036 FRM T05
sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read E2PROM Array Sequence (Figure 1). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 2). Write Sequence Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored. To write data to the E2PROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written.
The read only FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon power up. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide Programmable Hardware Write Protection (Table 2). When WP is LOW and the WPEN bit is programmed HIGH, all Status Register Write Operations are disabled. In Circuit Programmable ROM Mode This mechanism protects the Block Lock and Watchdog bits from inadvertant corruption. It may be used to perform an In Circuit Programmable ROM function by hardwiring the WP pin to ground, writing and Block Locking the desired portion of the array to be ROM, and then programming the WPEN bit HIGH. Read Sequence When reading from the E2PROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16bit address. After the READ opcode and address are
Table 2. Block Protect Matrix STATUS REGISTER WEL
0 1 1 1
STATUS REGISTER WPEN
X 1 0 X
DEVICE PIN WP#
X 0 X 1
BLOCK PROTECTED BLOCK
Protected Protected Protected Protected
BLOCK UNPROTECTED BLOCK
Protected Writable Writable Writable
STATUS REGISTER WPEN, BL0, BL1 WD0, WD1, BITS
Protected Protected Writable Writable
7036 FRM T06
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For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be "0" . While the write is in progress following a Status Register or E2PROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. RESET/RESET Operation The RESET (X25xx3) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the Watchdog timer has reached its programmable time-out limit. The RESET (X25xx5) output is designed to go HIGH whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time-out limit. Figure 1. Read E2PROM Array Sequence
The RESET/RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: * The device is in the low power standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is high impedance. * The Write Enable Latch is reset. * The Flag Bit is reset. * Reset Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: * A WREN instruction must be issued to set the Write Enable Latch. * CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
INSTRUCTION SI
16 BIT ADDRESS 15 14 13 3 2 1 0
DATA OUT HIGH IMPEDANCE SO 7 MSB 6 5 4 3 2 1 0
7036 FRM 03
5
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Figure 2. Read Status Register Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
INSTRUCTION SI
DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0
7036 FRM 04
Figure 3. Write Enable Latch Sequence
CS
0 SCK
1
2
3
4
5
6
7
SI
SO
HIGH IMPEDANCE
7036 FRM 05
6
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Figure 4. Write Sequence
CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION 16 BIT ADDRESS 15 14 13 3 2 1 0 7 6 5 DATA BYTE 1 4 3 2 1 0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
DATA BYTE 2
DAT A BYTE 3 1 0 7 6 5 4 3 2 1 0 6 5
DATA BYTE N 4 3 2 1 0
SI
7
6
5
4
3
2
7036 FRM 06
Figure 5. Status Register Write Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSTRUCTION SI 7 6 5
DATA BYTE 4 3 2 1 0
SO
HIGH IMPEDANCE
7036 FRM 07
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ........................-65C to +135C Storage Temperature .............................-65C to +150C Voltage on any Pin with Respect to VSS....... -1.0V to +7V D.C. Output Current ....................................................5mA Lead Temperature (Soldering, 10 seconds)............ 300C RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X25xxx-1.8 X25xxx-2.7 X25xxx Limits
1.8V-3.6V 2.7V to 5.5V 4.5V-5.5V
7036 FRM T08
Min.
0C -40C
Max.
70C +85C
7036 FRM T07
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits Symbol ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL(1) VIH VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLRS
(1)
Parameter VCC Write Current (Active) VCC Read Current (Active) VCC Standby Current WDT=OFF VCC Standby Current WDT=ON VCC Standby Current WDT=ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Reset Output LOW Voltage
Min.
Typ.
Max. 5 0.4 1 50 20
Units mA mA A A A A A V V V V V V V V
Test Conditions SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC =3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCCx0.7
10 10 VCCx0.3 VCC+0.5 0.4 0.4 0.4
VCC > 3.3V, IOL = 2.1mA 2V < VCC 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA
7036 FRM T09
VCC-0.8 VCC-0.4 VCC-0.2 0.4
V
POWER-UP TIMING Symbol
tPUR
(2) (2)
tPUW
Parameter Power-up to Read Operation Power-up to Write Operation
Min.
Max.
1 5
Units
ms ms
7036 FRM T10
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V. Symbol
COUT CIN
Notes:
(2) (2)
Test Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP)
Max.
8 6
Units
pF pF
Conditions
VOUT = 0V VIN = 0V
7036 FRM T11
(1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 8
X25643/45 X25323/25 X25163/65
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V 5V 3.3K
A.C. TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
7036 FRM T12
1.64K OUTPUT 1.64K 100pF RESET/RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Parameter Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time Voltage Range
2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 500 10
Min.
0 500 1000 250 500 250 500 200 400 200 400 50 50
Max.
2 1
Units
MHz ns ns ns ns ns ns ns
100 100
ns ns ns ms
7036 FRM T13
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Data Output Timing Symbol fSCK tDIS tV tHO tRO(3) tFO(3)
Notes:
Parameter Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
Voltage Range
2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V 2.7V-5.5V 1.8V-3.6V
Min.
0
Max.
2 1 250 200 400
Units
MHz ns ns ns
0 100 100
ns ns
7036 FRM T14
(3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
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Serial Output Timing
CS t CYC SCK tV SO MSB OUT MSB-1 OUT tHO t WL LSB OUT tDIS tWH t LAG
SI
ADDR LSB IN
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI t FI LSB IN tLAG
HIGH IMPEDANCE SO
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Power-Up and Power-Down Timing
VCC VTRIP 0 Volts tR RESET (X25643) tPURST tPURST tF tRPD V TRIP
RESET (X25645)
RESET Output Timing Symbol VTRIP tPURST tRPD(5) tF(5) tR(5) VRVALID
Notes:
Parameter Reset Trip Point Voltage, 5V Device Reset Trip Point Voltage, 2.7V Device Reset Trip Point Voltage, 1.8V Device Power-up Reset Timeout VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC
Min.
4.25 2.55 1.7 100
Typ.
Max.
4.5 2.7 1.8
Units
V V V ms ns ns ns V
7036 FRM T15
200
280 500
0.1 0.1 1
(5) This parameter is periodically sampled and not 100% tested.
CS vs. RESET/RESET Timing
CS t CST RESET t WDO tRST tWDO t RST
RESET
RESET/RESET Output Timing Symbol Parameter Watchdog Timeout Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Timeout Min.
100 450 1 400 100 200 300
Typ.
200 600 1.4
Max.
300 800 2
Units
ms ms sec ns ms
7036 FRM T16
tWDO
tCST tRST
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PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.10) 0.010 (0.25)
0.050" T ypical
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937)
0.250"
FOOTPRINT
0.030"Typical 14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
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8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X25643/45 X25323/25 X25163/65
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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ORDERING INFORMATION
X25643/45 X25323/25 X25163/65
P
T
-V VCC Limits Blank = 5V 10% 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package S14 = 14-Lead SOIC S8 = 8-Lead SOIC V14 = 14-Lead TSSOP
Device
Part Mark Convention X25643/45 X X Blank = 5V 10%, 0C to +70C I = 5V 10%, -40C to +85C F = 2.7V to 5.5V, 0C to +70C G = 2.7V to 5.5V, -40C to +85C AG = 1.8V to 3.6V, 0C to +70C Blank = 14-Lead SOIC X25323/25 X25163/65 X X Blank = 5V 10%, 0C to +70C I = 5V 10%, -40C to +85C F = 2.7V to 5.5V, 0C to +70C G = 2.7V to 5.5V, -40C to +85C AG = 1.8V to 3.6V, 0C to +70C Blank = 8-Lead SOIC V = 14 Lead TSSOP
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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